The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. CMOS devices have typically a transistor established by forming a gate electrode on a silicon substrate, and then forming a source region and a drain region side by side in the substrate beneath the gate electrode by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate is insulated from the source and drain regions by a thin gate oxide layer. This generally-described structure cooperates to function as a transistor.
To facilitate cooperation between the gate and the source and drain regions, most of the source and drain regions do not lie directly under the gate. However, a small part of the source region does overlap the gate, and likewise a small part of the drain region extends directly under the gate. These small parts of the source and drain regions that overlap the gate are respectively referred to as the lightly doped source/drain (LDD) regions.
While the LDD regions enhance the coupling between the gate and the channel that is established by the source and drain regions, the so-called “fringe” capacitive coupling is also induced between the gate and the LDD regions. Such fringe coupling degrades the performance of the transistor in alternating current (AC) applications. The importance of this consideration grows as the size of the transistors is reduced by ULSI technology, because while the overall dimensions of the transistors are smaller, the amount by which the LDD regions overlap the gate have heretofore remained unchanged. Accordingly, the undesirable effects of fringe capacitive coupling between the gate and the LDD regions are magnified in very small transistors.
One approach to the above-noted problem would be to reduce the dielectric constant of gate spacers, hence, reduce the capacitive coupling between the LDD regions and the gate.